ICS2O: FALL 2018
7. INDEPENDENT STUDY PROJECT
CLASS REFERENCE PROJECTS CONCEPTS SUPPLEMENTAL
39
Jan 18
Final Hardware Class
ISP Presentations
SA, AB, MC, ZC, JG, JK, LL, TM, HM, AM, LRC, JTP, ET, KT, RT, JV, NWS
JBe, PB, JBu, PC, JD, CG, MJ, SR, JS, LW
6, 7
38
Jan 16
Raman's Falstad
Counting Circuit
ISP Presentations
6, 7
37
Jan 14
ISP Presentations (Section 1 only)
6, 7
6. A COUNTING CIRCUIT
CLASS REFERENCE PROJECTS CONCEPTS SUPPLEMENTAL
36
Jan 10
Work Period

4b
Counting Circuits
SA, AB, MC, ZC, JG
JK, LL, TM*, HM, AM,
LRC**, JTP, ET, KT, RT
JV, NWS


JBe, PB*, JBu*, PC, MJ
JD**, CG, SR*, JS, LW
35
Jan 8
Fritzing:Stripboard
List of ISPs
4b
34
Dec 18
オープンソースでプログラムもできる、ニキシー管デジタル時計がアツい
Decade Counter Output as Input
to our THIRD Specialized IC:

The 4511 BCD to 7-Segment Decoder
Fola's Version
Click for

Interfacing Strategy
33
Dec 14
Digikey Order
(links to M. D by Saturday)
ISP Proposal Due
(handed to Mr. D at the START of the class)
Decade Counter Output as Clock Input
to our
SECOND Specialized IC:
The 4516 Up/Down (0-15) Counter
4b, 5
32
Dec 12
NGO Square Wave Output as Clock Input
to our
FIRST Specialized IC:
The 4017 Decade Counter
RSGC ACES: Decade Counter
4b
31
Dec 10
ISP Proposal
555 Tutorials
: #1, #2
(you want Astable mode)
LM555 Datasheet
Fun 555 Circuits
555 Calculator

Best 555 Tutorial
on the Web...
Eater's Astable 555

Logic Gates as
Memory (latch, flipflop) Elements
SR > D > FlipFlop
Combination
vs Sequential Logic Circuits: p.70
Comparators
Operational Amplifiers (OpAmps): p.71
FALSTAD: 555 Simulation
(Circuits > 555 Timer > Square Wave Generator)
4b
Counting (A&B)
SA*, AB, MC, ZC,
JK, LL, TM, HM, AM,
LRC, JTP, ET, KT, RT
JV, NWS
JBe, PB, JBu, PC,
JD*, CG, SR, JS, LW
30
Dec 6


The NAND Gate Oscillator (NGO)
Activity. NGO Part 2
Animations:
TP3, RC Drain
Activity: NGO Part 3 Fola's Version
4a
Fill/Drain Animations:
RC2-0.01uF, RC2-0.1uF
(Explore changes to RC2 components)

29
Dec 4

Grade Finals:
The Binary Game

AM vs PB
The NAND Gate Oscillator (NGO)
Activity. NGO Part 1
Animations: tp1, tp2, 3

4a

5. INTEGRATED CIRCUITS (ICs) I: DIGITAL LOGIC GATES
CLASS REFERENCE PROJECTS CONCEPTS SUPPLEMENTAL
28
Nov 30

Section Finals:
The Binary Game

Sec 1: AM
Sec 2: PB
NAND: The Universal Gate
The 4011 NAND Gate
NAND Gate Emulation:
NOT, OR, XOR
4a

AL: One busy elf!
27
Nov 28

Semis:
The Binary Game

Top 2 from each
Sec 1: AM, JTP
Sec 2: PB, JD
Combinational Logic Activties:
FALSTAD: Logic Gate IC Circuits

Multiple Input Gates
Gates as Operators: Boolean Arithmetic
The eXclusive OR (XOR) Gate
Activity. Addition-Related Logic Circuits
4a
Datasheet: CD4081
26
Nov 26

Don't try this@home...
Decapping ICs
Quarters:
The Binary Game

Top 4 from each move on
Sec 1: AM, JV, KT, JTP
Sec 2: JB,PB,JD,CG
Activity: Single input (Unary) Logic Gates
Breadboarding Tips for ICs
4a
The Analog Oscillator
SA, AB, MC, ZC, JG,
JK, LL, TM*, HM, AM,
LRC*, JTP, ET, KT, RT,
JV, NWS
JBe, PB, JBu, PC*, JD*,
CG, MJ, SR*, JS, LW
25
Nov 22
p. 47-48


The Binary Game
Top Scores
Sec 1: 3880 (AM)
Sec 2: 3160 (PB)
=TEXT(DEC2HEX(H5),"0000")
Role of Venn Diagrams
Digital Logic Gates - Truth Tables

4. DIGITAL FUNDAMENTALS
CLASS REFERENCE PROJECTS CONCEPTS SUPPLEMENTAL
24
Nov 20
Signed Binary:
The
2's Complement
Algorithm
The Binary Game
Top Scores
Sec 1: 2220 (AM)
Sec 2: 1710 (SR)
Number Systems: Binary (2)
Octal (8), Decimal (10), Hexadecimal (16)
Binary Representation of Characters:

ASCII Table, Unicode

23
Nov 14
p. 45
What is the difference between
Vcc, Vdd, Vee, Vss, etc?

Digital Name Pairs
, The Binary Number System
3
ISP Discussion
ISP Proposal
22
Nov 8


The Binary Game

Activity: Transistors as Logic Gates (TTL)
Venn Diagram of Number Sets...

Integers, Place Value

Analog (Continuous) vs Digital (Discrete)
Review of the Decimal Number System
The Capacitor Visualizer
SA, AB, MC, ZC, JG*,
JK, LL, TM, HM, AM,
LRC, JTP, ET, KT, RT,
JV, NWS
JBe, PB, JBu*, PC, JD,
CG, MJ, SR, JS, LW
3. TRANSISTORS
CLASS REFERENCE PROJECTS CONCEPTS SUPPLEMENTAL
21
Nov 6
2N3904 Datasheet
Build Session:
Project 3
. The Analog Oscillator
Falstad: Analog Oscillator Simulation
RSGC ACES: Astable Multivibrator
Research: The Astable Multivibrator

For Successful Builds...the early
Distribution of Additional Analog Oscillator Parts

Project 3.
The Analog Oscillator


20
Nov 2
Project 2. The Capacitor Visualizer
(due tomorrow)
Recall Diode-Resistor Logic...
Transistor-Transistor Logic: AND, OR
Transistor
Testing
Review/Discussion of Transistor Circuits

19
Oct 31

FALSTAD: Simple Transistor Circuit
Transistor Test Circuits
Automatic 'Knight' Light
  
18
Oct 29

pp. 33-36
Alternative NPNs:
PN2222A, BC547


The Best(?)
Transistor Introduction


2

  

Distribution of (additional) parts for
Project 2. The Capacitor Visualizer
Transistor
Basics, Testing, and Switches
What is to gain by knowing hFE?
The NPN Transistor (2N3904): Animation
The PNP Transistor (2N3906): Animation
Transistor Test Circuits
  
2. DESIGN, DIVIDERS, DEVICES and DATASHEETS
CLASS REFERENCE PROJECTS CONCEPTS SUPPLEMENTAL
17
Oct 25
2

Prototype Project 2. The Capacitor Visualizer
Begin to conduct required time trials

Introduction to Soldering
Solder long leads to your
PBNO, PBNC and Potentiometer

Solder your *NEW* DC Breakout Board



16
Oct 23
Review of Voltage Division Feedback Email
Measuring Capacitance with the DMM
Review Capacitor Circuits on page 32
Prototype the circuit to the left...
...and then the rollover modification
Capacitors as Timers
: `tau = R times C`
Voltage Division
SA, AB, MC, ZC, JG,
JK, LL, TM, HM, AM,
LRC, JTP, ET**, KT, RT,
JV, NWS
JBe, PB, JBu*, PC, JD*,
CG, MJ, SR, JS, LW
15
Oct 19
pp. 30-31
Capacitors

1

ER Guidelines

Identifying Capacitors
  
The Charge/Discharge Circuit
Unit of Measure: Farads, Ranges



14
Oct 17
The Underlying Principle of Digital Logic:
Pull-Down
and Pull-Up Resistor Configurations
LOGIC Functions: OR, AND
Diode-Resistor Logic (DRL)

13
Oct 15

Switch Basics
PBNO

PBNC

ACES' ER Technical Writing: Don'ts and Dos
Use of the Active Voice
Manual Input Devices:
Buttons: PBNO, PBNC
Switches (SPST, SPDT, DPDT)
Activities: Switch Circuit
Rocket Launch: RocketLaunchQuestion.fzz


Buttons and Switches

12
Oct 11
Advice:
Review TEL3M FC
Feedback Emails
Open House
(Period 2)
Format Painter, Styles, Headers
Footers, Image Prep and Alignment
Hanging Indent
ER Exemplar

11
Oct 9
1
Engineering Report: ACES' Grad Email

+ + +   = 
Show/Hide, Ruler, Tabs, Breaks, Styles
ER Guidelines

10
Oct 4
The Two Roles of the Potentiometer:
Variable Resistor and Voltage Divider
Two Sample Circuits to Demonstrate the two Roles

1. SIGNALS, SUPPLY, SYMBOLS, and SCHEMATICS
CLASS REFERENCE SUPPORT CONCEPTS SUPPLEMENTAL
9b
Oct 2
Summary of:
Signals, Supply, Symbols, and Schematics
9a
Oct 2
Circuit Analysis: LED Circuit
Introduction to Variable Resistors

Mechanical Potentiometers
Light-Dependent Resistors (LDRs)
Heat-Dependent Resistors (Thermistors)
Force-Sensitive Resistors (FSRs)
8
Sep 28
LED Datasheet
Waterfall Model (Continued)
The Concept of Voltage Division
DMM: Measuring Voltage and Amperage
Circuit Analysis
7
Sep 26
Circuit Analysis
Introduction to VOLTAGE
Waterfall Model of a Closed Circuit
Fundamental Circuit Laws
:
KVL: Kirchhoff's Voltage Law, `V=IR`, `P=IV`
 
6
Sep 24
`R_E=R_1+R_2`
`1/R_E=1/R_1+1/R_2`
ACES' Frame Player:
Resistor Circuits
Analysis of Fixed Resistors in Series and Parallel
Concept of: Equivalent Resistance (`R_E`)
Resistors.xlsx (...a little more math)

 
5
Sep 19
Voltage: `V=IR`
Power: `P=IV`
Ohm's Law
Analysis of Single Resistor Circuit
Resistors.xlsx (...a little math)
  
4
Sep 17
Digital Multimeter (DMM)
Circuit Symbols, Reading a Schematic
Useful Resistor Circuits
  
3
Sep 13
1-11
 
The Resistor Applet
Direction of Current, Anode and Cathode
Power: `P=IxxV`
Wire Gauge (p. 77), Greek Alphabet (p. 78)
Fixed (Current-Limiting) Resistors
2
Sep 11
Add F/C Conferences
ICS2O ISPs
Discussion: What is Electricity?
The Atom, Signals, Water Analogy, Flow Models
Giants of Electricity (p.81)
Supply: Voltage, Current (Direct and Alternating)
Direction of Current, Resistance
Circuit Symbols and Schematics
Reading a Schematic, Simple Resistor Circuits
How Semiconductors Work
1b
Sep 7
Nick Vassos:
Replacement Parts
Available in the Dragon's Lair 

Distribute Workbook
and Toolkit
Starters are a dime-a-dozen...
Student Reflections
Why is this Course Necessary? The Workbook?
Technical Advisors, Acknowledgements
ACES: A Focus on Skills, Table of Contents
1a
Sep 7
Student Outline
Mr. D's Schedule
REPUTATION and RESPECT
RSGC ACES CULTURE: Taking a
Short, Medium, and Long Term View
of your Futures

ACES Hall of Fame:
E. McAulliffe ('18), Mariano Elia ('15), Jack Gettings ('10)

[ACES Culture]

For our second Field Trip of the year we have been invited to visit a factory that is developing solar panels. Since this device is an integral part of our Greenhouse Project this year, early familiarity with this technology will be advantageous.
What better way is there to start the year than with a walking field trip to acquire the electronic components that we will make good use of? You'll also be aware of its location for your own personal projects.
I have no formal training in electronics or electrical engineering - I'm just really interested in this field. The knowledge and skill I have has been largely acquired over the last few years from learning alongside many talented Georgians and I look forward to expanding my capabilities by working with you this year.
I ask six things of my ACES (for most other things I'm usually flexible):
1. SHORTCUTS. The world has enough corner-cutters. This is includes cheating, plagiarizing, or lying.
2. SHARED SPACE. Show respect for others that use the lab by putting your projects away and leaving your bench area tidy when you leave.
3. DES VISITORS. Show respect for adult visitors that enter the lab by immediately stopping what you are doing, standing and facing the individual(s).
4. NO EATING. Show respect for the lab by not eating in the DES. You may go into the hallway for a quick bite if you need to.
5. AVOID WASTE. Show respect for the lab's resources by not wasting or misusing them.
6. REPUTATION. Show respect for yourself by looking (and speaking) your best. It's the little things keep the doors of opportunity open.
  1. Matches will last exactly 5 minutes
  2. Two qualifying rounds (average points) will determine the initial Tournament seeding
  3. The top 8 seeds move on into the quarter-finals
  4. The Term 1 winner will play the winner of Term 2 in May to determine the Grade winner
  5. The Grade 10 winner will play one match against Mike Ciomyk to determine the 2015 School Champion
  6. Technical problems of any sort with your laptop during a match results in immediate disqualification from the match
Growing Success, p. 29
Responsibility, Organization, Independent Work, Collaboration, Initiative, Self-Reliant Growing Success. p.11.

It is worth noting, right from the start, that assessment is a human process, conducted by and with human beings, and subject inevitably to the frailties of human judgement.
However crisp and objective we might try to make it, and however neatly quantifiable may be our "results", assessment is closer to art than science.
It is, after all, an exercise in human communication.
Knowledge: Subject-specific content acquired in each course (knowledge), and the comprehension of its meaning and significance (understanding).
Thinking: The use of critical and creative thinking skills and/or processes, as follows:
Communication: The conveying of meaning through various forms, as follows:
Application: The use of knowledge and skills to make connections within and between various contexts.