ICS2O: FALL 2018 | ||||
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7. INDEPENDENT STUDY PROJECT |
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CLASS | REFERENCE | PROJECTS | CONCEPTS | SUPPLEMENTAL |
39 Jan 18 |
Final Hardware Class |
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38 Jan 16 |
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37 Jan 14 |
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CLASS | REFERENCE | PROJECTS | CONCEPTS | SUPPLEMENTAL |
36 Jan 10 |
Work Period
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35 Jan 8 |
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34 Dec 18 |
オープンソースでプログラムもできる、ニキシー管デジタル時計がアツい
Decade Counter Output as Input to our THIRD Specialized IC: The 4511 BCD to 7-Segment Decoder Fola's Version |
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33 Dec 14 |
ISP Proposal Due (handed to Mr. D at the START of the class) Decade Counter Output as Clock Input to our SECOND Specialized IC: The 4516 Up/Down (0-15) Counter |
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32 Dec 12 |
NGO Square Wave Output as Clock Input to our FIRST Specialized IC: The 4017 Decade Counter RSGC ACES: Decade Counter |
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31 Dec 10 |
ISP Proposal 555 Tutorials: #1, #2 (you want Astable mode) LM555 Datasheet Fun 555 Circuits 555 Calculator |
Best 555 Tutorial |
Logic Gates as Memory (latch, flipflop) Elements SR > D > FlipFlop Combination vs Sequential Logic Circuits: p.70 Comparators Operational Amplifiers (OpAmps): p.71 FALSTAD: 555 Simulation (Circuits > 555 Timer > Square Wave Generator) |
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30 Dec 6 |
The NAND Gate Oscillator (NGO) Activity. NGO Part 2 Animations: TP3, RC Drain Activity: NGO Part 3 Fola's Version |
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29 Dec 4 |
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5. INTEGRATED CIRCUITS (ICs) I: DIGITAL LOGIC GATES |
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CLASS | REFERENCE | PROJECTS | CONCEPTS | SUPPLEMENTAL |
28 Nov 30 |
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27 Nov 28 |
Combinational Logic Activties:
FALSTAD: Logic Gate IC Circuits Multiple Input Gates Gates as Operators: Boolean Arithmetic The eXclusive OR (XOR) Gate Activity. Addition-Related Logic Circuits |
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26 Nov 26 |
Activity: Single input (Unary) Logic Gates
Breadboarding Tips for ICs |
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25 Nov 22 |
p. 47-48 |
=TEXT(DEC2HEX(H5),"0000")
Role of Venn Diagrams Digital Logic Gates - Truth Tables |
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4. DIGITAL FUNDAMENTALS |
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CLASS | REFERENCE | PROJECTS | CONCEPTS | SUPPLEMENTAL |
24 Nov 20 |
Signed Binary: The 2's Complement Algorithm |
Number Systems:
Binary (2) Octal (8), Decimal (10), Hexadecimal (16) Binary Representation of Characters: ASCII Table, Unicode |
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23
Nov 14 |
p. 45 |
What is the difference between Vcc, Vdd, Vee, Vss, etc? Digital Name Pairs, The Binary Number System |
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22 Nov 8 |
Activity: Transistors as Logic Gates (TTL) Venn Diagram of Number Sets... Integers, Place Value Analog (Continuous) vs Digital (Discrete) Review of the Decimal Number System |
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3. TRANSISTORS |
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CLASS | REFERENCE | PROJECTS | CONCEPTS | SUPPLEMENTAL |
21 Nov 6 |
2N3904 Datasheet Build Session: Project 3. The Analog Oscillator Falstad: Analog Oscillator Simulation RSGC ACES: Astable Multivibrator Research: The Astable Multivibrator For Successful Builds...the early |
Project 3. The Analog Oscillator |
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20 Nov 2 |
Project 2. The Capacitor Visualizer (due tomorrow) Recall Diode-Resistor Logic... Transistor-Transistor Logic: AND, OR Transistor Testing Review/Discussion of Transistor Circuits |
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19 Oct 31 |
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18 Oct 29 |
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2. DESIGN, DIVIDERS, DEVICES and DATASHEETS |
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CLASS | REFERENCE | PROJECTS | CONCEPTS | SUPPLEMENTAL |
17 Oct 25 |
Prototype Project 2. The Capacitor Visualizer Begin to conduct required time trials Introduction to Soldering Solder long leads to your PBNO, PBNC and Potentiometer Solder your *NEW* DC Breakout Board |
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16 Oct 23 |
Review of Voltage Division Feedback Email Measuring Capacitance with the DMM Review Capacitor Circuits on page 32 Prototype the circuit to the left... ...and then the rollover modification Capacitors as Timers: `tau = R times C` |
Voltage Division SA, AB, MC, ZC, JG, JK, LL, TM, HM, AM, LRC, JTP, ET**, KT, RT, JV, NWS JBe, PB, JBu*, PC, JD*, CG, MJ, SR, JS, LW |
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15 Oct 19 |
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14 Oct 17 |
The Underlying Principle of Digital Logic: Pull-Down and Pull-Up Resistor Configurations LOGIC Functions: OR, AND Diode-Resistor Logic (DRL) |
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13 Oct 15 |
ACES' ER Technical Writing: Don'ts and Dos Use of the Active Voice Manual Input Devices: Buttons: PBNO, PBNC Switches (SPST, SPDT, DPDT) Activities: Switch Circuit Rocket Launch: RocketLaunchQuestion.fzz |
Buttons and Switches |
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12 Oct 11 |
Advice:
Review TEL3M FC Feedback Emails |
Open House (Period 2) |
ER Exemplar |
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11 Oct 9 |
ER Guidelines |
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10 Oct 4 |
The Two Roles of the Potentiometer: Variable Resistor and Voltage Divider Two Sample Circuits to Demonstrate the two Roles |
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1. SIGNALS, SUPPLY, SYMBOLS, and SCHEMATICS |
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CLASS | REFERENCE | SUPPORT | CONCEPTS | SUPPLEMENTAL |
9b Oct 2 |
Summary of: Signals, Supply, Symbols, and Schematics |
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9a Oct 2 |
Circuit Analysis: LED Circuit Introduction to Variable Resistors Mechanical Potentiometers Light-Dependent Resistors (LDRs) Heat-Dependent Resistors (Thermistors) Force-Sensitive Resistors (FSRs) |
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8 Sep 28 |
Waterfall Model (Continued) The Concept of Voltage Division DMM: Measuring Voltage and Amperage Circuit Analysis |
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7 Sep 26 |
Introduction to VOLTAGE Waterfall Model of a Closed Circuit Fundamental Circuit Laws: KVL: Kirchhoff's Voltage Law, `V=IR`, `P=IV` |
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6 Sep 24 |
`R_E=R_1+R_2`
`1/R_E=1/R_1+1/R_2` |
ACES' Frame Player: Resistor Circuits |
Analysis of Fixed Resistors in Series and Parallel Concept of: Equivalent Resistance (`R_E`) Resistors.xlsx (...a little more math) |
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5 Sep 19 |
Voltage: `V=IR`
Power: `P=IV` |
Ohm's Law |
Analysis of Single Resistor Circuit Resistors.xlsx (...a little math) |
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4 Sep 17 |
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3 Sep 13 |
1-11 |
Direction of Current, Anode and Cathode Power: `P=IxxV` Wire Gauge (p. 77), Greek Alphabet (p. 78) Fixed (Current-Limiting) Resistors |
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2 Sep 11 |
Discussion:
What is Electricity? The Atom, Signals, Water Analogy, Flow Models Giants of Electricity (p.81) Supply: Voltage, Current (Direct and Alternating) Direction of Current, Resistance Circuit Symbols and Schematics Reading a Schematic, Simple Resistor Circuits How Semiconductors Work |
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1b Sep 7 |
Distribute Workbook and Toolkit |
Starters are a dime-a-dozen... Student Reflections Why is this Course Necessary? The Workbook? Technical Advisors, Acknowledgements ACES: A Focus on Skills, Table of Contents |
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1a Sep 7 |
REPUTATION and RESPECT RSGC ACES CULTURE: Taking a Short, Medium, and Long Term View of your Futures ACES Hall of Fame: E. McAulliffe ('18), Mariano Elia ('15), Jack Gettings ('10) |
[ACES Culture] |