Thursday January 17. FINAL EXAM

• Please arrive in class as soon after Period 1 as possible. The exam will start at 9:35am, run through most of the break, and end at 11:05am (90 minutes). The last 10 minutes will enable all ERs to be submitted to handin, all circuits and extra wire kits to be collected
• You are to bring the following into the exam,
  • your fully charged laptop
  • your up-to-date Engineering Report (ER.docx)
  • your Evil Genius workbook and toolkit
  • your working prototype of the circuit depicted in Figure L26-1 on page 99
  • your reliable, working 12V power supply
  • pencil and paper, just in case
• Further details will be provided in class.

Friday December 7. DIGITAL LOGIC.

• Online (similar to the previous test)
• 20 objectives questions: 10 multiple choice and 10 true/false questions
• Ensure you are familiar with (in no particular order)
  • The binary number system for whole numbers up to and including 255 (decimal)
  • The ASCII values for: space (32), '0' (48), 'A' (65), and 'a' (97)
  • The sizes of data (in bits): bit (1), nybble (4), byte (8), word (16), double word (32), quad word (64)
  • The digital logic gates (2 unary gates: EQU & NOT) and (4 binary gates: AND, OR, NAND, NOR)
  • The analog circuits equivalent to the digital logic gates
  • The gate symbols for the digital logic gates
  • The design (orientation, pin assignments) of CMOS 14-pin DIP packages
  • The truth tables for the digital logic gates